A 2.89mW 50GOPS 16×16 16-core MIMO sphere decoder in 90nm CMOS

@article{Yang2009A25,
  title={A 2.89mW 50GOPS 16×16 16-core MIMO sphere decoder in 90nm CMOS},
  author={Chia-Hsiang Yang and Dejan Markovic},
  journal={2009 Proceedings of ESSCIRC},
  year={2009},
  pages={344-347}
}
A 16-core multi-input multi-output (MIMO) decoder for agile communication systems is implemented in a low-VT 90nm CMOS technology. This chip implements the sphere decoding algorithm and is highly flexible to support multiple configurations: antenna arrays from 2×2 to 16×16, modulations from BPSK to 64QAM, and up to 128 data streams. Operating at 16MHz, the chip provides 50GOPS (12-bit add equivalent) in the 16×16, 64QAM mode. It consumes 2.89mW of power with a 321mV supply voltage, resulting in… CONTINUE READING
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