A 2.7 ns 0.25 /spl mu/m CMOS 54/spl times/54 b multiplier

  title={A 2.7 ns 0.25 /spl mu/m CMOS 54/spl times/54 b multiplier},
  author={Yoshio Hagihara and Shigeto Inui and Akihiko Yoshikawa and Shu Nakazato and S. Iriki and Ryosuke Ikeda and Y. Shibue and Takehito Inaba and M. Kagamihara and Masakazu Yamashina},
  journal={1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)},
A 0.25 /spl mu/m CMOS 2.7 ns latency multiplier capable of supporting a 400 MHz double-stage pipelined FPU consists of Booth recoders, partial product generators, a 4-to-2 compressor tree, and a 108 b final adder. The 4-to-2 compressor combines dual-rail domino and pass-transistor logic gates. The compressor consists of two carry-save adders (CSAs = full adders), and each of the CSAs includes two domino gates for generating carries and a pass-transistor logic gate for generating sums. The… CONTINUE READING


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