A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS

@article{Verbruggen2010A2M,
  title={A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS},
  author={Bob Verbruggen and Jan Craninckx and Maarten Kuijk and Piet Wambacq and Geert Van der Plas},
  journal={IEEE Journal of Solid-State Circuits},
  year={2010},
  volume={45},
  pages={2080-2090}
}
A 2.2 GS/s 4×-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. The folding stage samples the input, removes its common-mode component and rectifies the differential voltage. The pipelined binary-search sub-ADC leverages threshold calibration to correct for amplifier and comparator imperfections, which allows the use of… CONTINUE READING
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