A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging

@article{Chen2017A2B,
  title={A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging},
  author={Poki Chen and Ya-Yun Hsiao and Yi-Su Chung and Wei Xiang Tsai and Jhih-Min Lin},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2017},
  volume={25},
  pages={114-124}
}
A high-resolution time-to-digital converter (TDC) implemented with field programmable gate array (FPGA) based on delay wrapping and averaging is presented. The fundamental idea is to pass a single clock through a series of delay elements to generate multiple reference clocks with different phases for input time quantization. Due to periodicity, those phases… CONTINUE READING