A 2.5 Gbps - 3.125 Gbps multi-core serial-link transceiver in 0.13 /spl mu/m CMOS

  title={A 2.5 Gbps - 3.125 Gbps multi-core serial-link transceiver in 0.13 /spl mu/m CMOS},
  author={T. Geurts and Willen Rens and Jan Crols and Shoichiro Kashiwakura and Yuichiro Segawa},
  journal={Proceedings of the 30th European Solid-State Circuits Conference},
A multi-rate serdes macro that is targeting multi-channel applications has been developed in 0.13 /spl mu/m. A low-jitter LC VCO PLL can provide the master clock for up to 16 receive and transmit modules. Specific provisions for operation at different data rates are present. The receive module operates at full rate. Comma detection and 8b/10b coding are present. The transmitter has a measured output jitter of 8.1 ps rms at 2.5 Gbps. The receiver has a measured intrinsic jitter tolerance of 0.75… CONTINUE READING


Publications citing this paper.
Showing 1-10 of 11 extracted citations

A 12Gbps all digital low power SerDes transceiver for on-chip networking

2011 IEEE International Symposium of Circuits and Systems (ISCAS) • 2011
View 6 Excerpts
Highly Influenced

Implementation of 10bit SerDes for Gigabit Ethernet PHY

2015 International Conference on Man and Machine Interfacing (MAMI) • 2015
View 1 Excerpt

A 19 mW/lane Serdes transceiver for SFI-5.1 application

2011 IEEE Custom Integrated Circuits Conference (CICC) • 2011
View 1 Excerpt

A Comma Detection and Word Alignment Circuit for High-Speed SerDes

2011 7th International Conference on Wireless Communications, Networking and Mobile Computing • 2011


Publications referenced by this paper.
Showing 1-5 of 5 references

A quad 3.125 Ghisichannel transceiver with analog phase rotators,

Dong Zheng
International Solid-Stafe Circuits Conference, Digest of Technical Papers, • 2002

5 Gbis bidirectional halancedline link compliant with plesiochronous clocking,

H. Tamura
International Solid-state Circuits Conference, Digest of Technical Papers, • 2001

Prospects of CMOS technology for high-speed optical communication circuits

GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191) • 2001

A fully integrated SiGe receiver IC for 10 Gb/s data rate

2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056) • 2000

Similar Papers

Loading similar papers…