A 2.5 Gbps - 3.125 Gbps multi-core serial-link transceiver in 0.13 /spl mu/m CMOS

@article{Geurts2004A2G,
  title={A 2.5 Gbps - 3.125 Gbps multi-core serial-link transceiver in 0.13 /spl mu/m CMOS},
  author={T. Geurts and Willen Rens and Jan Crols and Shoichiro Kashiwakura and Yuichiro Segawa},
  journal={Proceedings of the 30th European Solid-State Circuits Conference},
  year={2004},
  pages={487-490}
}
A multi-rate serdes macro that is targeting multi-channel applications has been developed in 0.13 /spl mu/m. A low-jitter LC VCO PLL can provide the master clock for up to 16 receive and transmit modules. Specific provisions for operation at different data rates are present. The receive module operates at full rate. Comma detection and 8b/10b coding are present. The transmitter has a measured output jitter of 8.1 ps rms at 2.5 Gbps. The receiver has a measured intrinsic jitter tolerance of 0.75… CONTINUE READING

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