A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-/spl mu/m CMOS

@article{Beek2004A2C,
  title={A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-/spl mu/m CMOS},
  author={R. C. H. van de Beek and C. S. Vaucher and D. M. W. Leenaerts and E. A. M. Klumperink and Bram Nauta},
  journal={IEEE Journal of Solid-State Circuits},
  year={2004},
  volume={39},
  pages={1862-1872}
}
This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in… CONTINUE READING
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