A 2.4-GHz Low-Power All-Digital Phase-Locked Loop

@article{Xu2009A2L,
  title={A 2.4-GHz Low-Power All-Digital Phase-Locked Loop},
  author={Liangge Xu and Saska Lindfors and Kari Stadius and Jussi Ryyn{\"a}nen},
  journal={2009 IEEE Custom Integrated Circuits Conference},
  year={2009},
  pages={331-334}
}
This paper presents an all-digital phase-locked loop (ADPLL) for the 2.4-GHz ISM band frequency synthesis. The ADPLL is built around a digitally controlled LC oscillator. In the feedback path, a high-speed topology is employed for the variable phase accumulator to count full cycles of the RF output. A simple technique based on a short delay line in the reference signal path allows the time-to-digital converter core to operate at a low duty cycle with about 95% reduction of its average power… CONTINUE READING
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