A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC

@inproceedings{Wong2012A21,
  title={A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC},
  author={S. Wong and U. Chio and Yan Zhu and Sai-Weng Sin and U. Seng-Pan and R. Martins},
  booktitle={CICC},
  year={2012}
}
A 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC architecture is proposed, where the ADC's front-end is built with a 5b binary-search ADC, shared by two time-interleaved 6b SAR ADCs in the 2nd-stage. The design prevents the use of opamp that causes large power dissipation. Besides, a process insensitive asynchronous logic is proposed to further reduce the delay of SA loop. The ADC was fabricated in 65nm CMOS and achieves 54.6dB SNDR at 170MS/s with only 2.3mW of power… Expand
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