A 2.2 GOPS video DSP with 2-RISC MIMD, 6-PE SIMD architecture for real-time MPEG2 video coding/decoding

@article{Iwata1997A2G,
  title={A 2.2 GOPS video DSP with 2-RISC MIMD, 6-PE SIMD architecture for real-time MPEG2 video coding/decoding},
  author={Eiji Iwata and Katsunori Seno and Masayoshi Aikawa and Mitsuharu Ohki and Hiroshi Yoshikawa and Yoshiaki Fukuzawa and Hirofumi Hanaki and Kento Nishibori and Yuji Kondo and H. Takamuki and Taku Nagai and Kouichi Hasegawa and Hiroshi Okuda and I. Kumata and M. Soneda and Shigehito Iwase and Tomoyuki Yamazaki},
  journal={1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers},
  year={1997},
  pages={258-259}
}
In multimedia applications, various video encoding/decoding standards such as MPEG2, MPEG1 and emerging algorithms call for a DSP solution of the extremely computation-intensive tasks. Several DSPs have been developed based on intensive pipeline processing at the macro-block level. In these DSPs, macroblock-based pipeline memory slices are needed for each pipeline stage. Programmability is limited by the hard-wired macros to be incorporated such as DCT and Quantizer. A microprocessor or a media… CONTINUE READING

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