A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes

Abstract

This paper proposes a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder… (More)
DOI: 10.1109/TCSI.2012.2230506

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