A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin


A 90nm CMOS, 64Kbit, 1.16GHz, 16 port SRAM with multi-bank architecture realizing 590Gbps random access bandwidth, 41mW power dissipation at 1GHz and 0.91mm2 (13.9μm2/bit) area consumption is reported. Compared to conventional 16 port SRAM data, area and power consumption are reduced by factors 16 and 5, respectively, while maximum clock frequency is about… (More)
DOI: 10.1587/elex.4.21


3 Figures and Tables