A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers

@article{Zerbe2001A2G,
  title={A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers},
  author={J. Zerbe and P. S. Chau and C. Werner and W. F. Stonecypher and H. J. Liaw and Gong Jong Yeh and T. P. Thrush and S. Best and K. Donnelly},
  journal={2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)},
  year={2001},
  pages={66-67}
}
  • J. Zerbe, P.S. Chau, +6 authors K. Donnelly
  • Published 2001
  • Computer Science
  • 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)
  • A 2 Gb/s/pin single-ended 4-PAM parallel bus interface uses transmit crosstalk cancellation and equalization techniques as well as integrating data receivers to improve system margin in low-cost packaging despite inherent coupling noise and data distortion. 

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