A 2.5V 10b 120 MSample/s CMOS Pipelined ADC with high SFDR

Abstract

A 10b multibit-per-stage pipelined ADC incorporating merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are ±0.40 LSB and ±0.48 LSB, respectively. The ADC fabricated in a 0.25 μm CMOS occupies 3.6 mm active die area and consumes 208 mW under a 2.5V power supply. Introduction The dramatic growth in the high-tech sector of the consumer market has created many unprecedented challenges in the area of integrated circuits. The present and future communication systems including high-speed modems and broadband wired and wireless communication subsystems require increasingly higher performance ADCs. The required level of accuracy can exceed 10b at conversion speed of hundreds of megahertz. The pipelined architecture has been widely employed to meet the required performance in this arena due to properly managed trade-off between speed, power consumption, and die area (1)-(7). The CMOS ADCs recently reported with a sampling rate above 50 MSample/s at more than 10b resolution are illustrated in Fig. 1 (1)-(9). A parallel pipeline ADC (5) demonstrated the 46 dB total harmonic distortion at 200 MSample/s with a 0.5um CMOS process, and some mismatches between four channels degraded the full dynamic performance of the ADC. This work describes design considerations for a new multibitper-stage pipelined ADC architecture that has resulted in a single-channel 10b 120 MSample/s performance. This prototype includes the IC realization of the merged-capacitor switching (MCS) technique, which enjoys the benefit of employing only 8 unit-size capacitors for a 4-bit multiplying analog-to-digital converter (MDAC) instead of 16 capacitors normally required in the conventional MDAC architecture (10). Proposed ADC Architecture The block diagram of the proposed 10b pipelined ADC is illustrated in Fig. 2. It is based on a conventional three-stage pipelined architecture. The ADC consists of an input sampleand-hold amplifier (SHA), two 4b MDACs, three 4b subranging flash ADCs, and some extra supporting circuit * Currently with Samsung Electronics Co., Suwon, Korea. SPEED (MSample/s) R ES O LU TI O N (b it) ISSCC 1997 (9) ISSCC 2000 (7) ISSCC 2001 (4)

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Cite this paper

@inproceedings{Yoo2002A21, title={A 2.5V 10b 120 MSample/s CMOS Pipelined ADC with high SFDR}, author={Sang-Min Yoo and Tae-Hwan Oh and Jung-Woong Moon and Seung-Hoon Lee and Un-Ku Moon}, year={2002} }