A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvement

@article{Tsai2014A1I,
  title={A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvement},
  author={Jen-Huan Tsai and Sheng-An Ko and Hui-Huan Wang and Chia-Wei Wang and Hsin Chen and Po-Chiun Huang},
  journal={2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)},
  year={2014},
  pages={233-236}
}
This paper presents a low-area, high-efficiency hybrid 6-stage voltage multiplier by cascoding Dickson chargepumps and modified Cockcroft-Walton charge-pumps, and paralleling them with auxiliary charge-pumps. The proposed architecture obtains a good area and efficiency performance without using high-V devices or external capacitors. Implemented in a standard 0.18-μm CMOS process, the prototype provides a wide output range of 3-6V and 30-240μA load from a 1-V supply with an efficiency of 48-58… CONTINUE READING