A 1GS/s low-power low-kickback noise comparator in CMOS process

@article{Baradaranrezaeii2011A1L,
  title={A 1GS/s low-power low-kickback noise comparator in CMOS process},
  author={Ali Baradaranrezaeii and Roozbeh Abdollahi and Khayrollah Hadidi and Abdollah Khoei},
  journal={2011 20th European Conference on Circuit Theory and Design (ECCTD)},
  year={2011},
  pages={106-109}
}
A high speed comparator based on a high DC-gain folded-cascode amplifier is presented. Four switches rearrange the structure to speed up the comparison process and prevent kickback noise with a simple set of controlling signals. The circuit is a rail-to-rail folded-cascode amplifier during reset/evaluation period which transforms into two back-to-back inverters during the latch period to speed up the settling. The reset and the evaluation sequences are merged due to the special structure… CONTINUE READING

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