A 19 nm 112.8 mm$^{2}$ 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface

@article{Kanda2013A1N,
  title={A 19 nm 112.8 mm\$^\{2\}\$ 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface},
  author={Kazushige Kanda and Noboru Shibata and Toshiki Hisada and Katsuaki Isobe and Manabu Sato and Yui Shimizu and Takahiro Shimizu and Takahiro Sugimoto and Tomohiro Kobayashi and Naoaki Kanagawa and Yasuyuki Kajitani and Takeshi Ogawa and Kiyoaki Iwasa and Masatsugu Kojima and Toshihiro Suzuki and Yuya Suzuki and Shintaro Sakai and Tomofumi Fujimura and Yuko Utsunomiya and Toshifumi Hashimoto and Naoki Kobayashi and Yuuki Matsumoto and Satoshi Inoue and Yoshinao Suzuki and Yasuhiko Honda and Yosuke Kato and Shingo Zaitsu and Hardwell Chibvongodze and Mitsuyuki Watanabe and Hong Ding and Naoki Ookuma and Ryuji Yamashita},
  journal={IEEE Journal of Solid-State Circuits},
  year={2013},
  volume={48},
  pages={159-167}
}
A 64 Gb MLC NAND flash memory in 19 nm CMOS technology has been developed. By adopting one-sided all bit line (ABL) architecture, the single cell array configuration, bit line bias acceleration (BLBA) and BC states first program algorithm, the smallest 64 Gb die size in 2 bit/cell is achieved with high performance of 15 MB/s program throughput. Program suspend and erase suspend functions are introduced to improve the read latency. High speed toggle mode interface of 400 Mbit/sec/pin at VCCQ = 1… CONTINUE READING