A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC

@article{Deguchi2013A15,
  title={A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC},
  author={Jun Deguchi and Fumihiko Tachibana and Makoto Morimoto and Masayoshi Chiba and Takeshi Miyaba and Hideki Tanaka and Kyoichi Takenaka and Satoshi Funayama and Kunihiko Amano and Kazuhide Sugiura and Ryuta Okamoto and Shouhei Kousai},
  journal={2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers},
  year={2013},
  pages={494-495}
}
Low-power and small-area implementations are essential in the mobile-phone market. Serial signal-processing architectures, in which signal-processing circuits such as a programmable-gain amplifier (PGA) and an ADC can be shared by column-level correlated double sampling (CDS) circuits, promise to reduce chip size and power consumption. However, conventional column CDS circuits composed of linear capacitors or NMOS capacitors (NMOSCAPs) with output buffers (OBUFs) still occupy a large footprint… CONTINUE READING