A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture

@article{Miyazaki2002A1M,
  title={A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture},
  author={Masaya Miyazaki and J. Kao and A. P. Chandrakasan},
  journal={2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)},
  year={2002},
  volume={1},
  pages={58-444 vol.1}
}
The power dissipation of a digital circuit is minimized by simultaneous control of power supply voltage and body bias. The technique minimizes power dissipation for varying processing rates through dynamic adjustment of V/sub dd/ and V/sub tb/. A 16b MAC operates at 166 kHz and 14 nW at 175 mV V/sub dd/. A ring oscillator operates at 0.1 V. 
Highly Cited
This paper has 424 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 161 extracted citations

Interests and Limitations of Technology Scaling for Subthreshold Logic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems • 2009
View 5 Excerpts
Highly Influenced

Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring

IEEE International Conference on Test, 2005. • 2005
View 8 Excerpts
Method Support
Highly Influenced

Mixed-signal CPM controlled DC-DC converter IC with embedded power management for digital loads

2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC) • 2013
View 6 Excerpts
Highly Influenced

Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial

IEEE Transactions on Circuits and Systems I: Regular Papers • 2012
View 4 Excerpts
Highly Influenced

424 Citations

02040'00'04'09'14'19
Citations per Year
Semantic Scholar estimates that this publication has 424 citations based on the available data.

See our FAQ for additional information.

References

Publications referenced by this paper.
Showing 1-10 of 20 references

A 1.2-GIPS/W microprocessor using speed-adaptive theshold-voltage CMOS with forward bias

M. Miyazaki
IEEE J. Solid-State Circuits, vol. 37, pp. 210–217, Feb. 2002. • 2002
View 2 Excerpts

A 175 mV multiply-accumulate unit using an Adaptive Supply Voltage and Body Bias (ASB) architecture

M. Miyazaki, J. Kao, A. Chandraksan
inISSCC Dig. Tech. Papers , Feb. 2002, pp. 58–59. • 2002
View 1 Excerpt

Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) • 2002
View 1 Excerpt

A dynamic voltage scaled microprocessor system

IEEE Journal of Solid-State Circuits • 2000
View 1 Excerpt

A new technique for standby leakage reduction in high-performance circuits

Y. Ye, S. Borkar, V. De
inProc. 1998 Symp. VLSI Circuits , June 1998, pp. 40–41. • 1998
View 1 Excerpt