A 16mb Dram with an Open Bit-Line Architecture

@article{Inoue1988A1D,
  title={A 16mb Dram with an Open Bit-Line Architecture},
  author={M. Inoue and H. Kotani and T. Yamada and H. Yamauchi and A. Fujiwara and J. Matsushima and H. Akamatsu and M. Fukumoto and M. Kubota and I. Nakao and N. Aoi and G. Fuse and S. Ogawa and S. Odanaka and A. Ueno and H. Yamamoto},
  journal={1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers},
  year={1988},
  pages={246-}
}
  • M. Inoue, H. Kotani, +13 authors H. Yamamoto
  • Published 1988
  • Engineering, Computer Science
  • 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers
THIS PAPER WILL COVER A 16Mb DRAM with a 6511s RAS access time and 5.4mm x 17.38mm (93.85mm2) chip in a 300mil dual-in-line package. The chip was fabricated in 0 . 5 ~ N-well CMOS technology with double-poly, single-polycide and double-metal. To package a 16Mb DRAM in a 300mil DIP, the memory cell size has t o be less than 4pm2 maintaining a capacitance large enough for alpha-particle-induced soft error tolerance and the stable operation. Open bit-line architecture can provide a small geometry… Expand
A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture
TLDR
A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. Expand
A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register
A single 3.3-V 16-Mbit DRAM with a 135-mm/sup 2/ chip size has been fabricated using a 0.5- mu m twin-well process with double-metal wiring. The array architecture, based on the twisted-bit-lineExpand
A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure
Low-noise, high-speed circuit techniques for high-density DRAMs (dynamic random-access memories), as well as their application to a single 5-V 16-Mb CMOS DRAM with a 3.3-V internal operating voltageExpand
Twisted bit-line architectures for multi-megabit DRAMs
TLDR
Twisted bit-line architectures to reduce or eliminate the noise are proposed and demonstrated by the soft-error rate improvement of a 1-Mb DRAM, and they are shown to be promising candidates for overcoming the scaling problems of DRAMs. Expand
Trends in megabit DRAM circuit design
The state of the art in megabit dynamic random access memory (DRAM) circuit and chip design is reviewed in terms of essential design parameters such as signal-to-noise ratio, power dissipation, andExpand
A divided/shared bit-line sensing scheme for ULSI DRAM cores
A new dynamic RAM (DRAM) signal sensing principle, a divided/shared bit-line (DSB) sensing scheme, is proposed. This sensing scheme provides folded bit-line sensing operation in a crosspoint-typeExpand
An experimental 16-Mbit DRAM with reduced peak-current noise
An experimental 16-Mbit CMOS DRAM with die size of 8.52 X18.4 mm2 has been developed. A trenched and saddled stack capacitor (TSSC) cell was invented, and storage capacitance of 30fF was obtained inExpand
A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's
This paper describes a novel circuit technology with Surrounding Gate Transistors (SGT's) For ultra high density DRAM's. In order to reduce the chip size drastically, an SGT is employed to all theExpand
A 16Mbit DRAM Test Device
  • W. Raab, M. Beurer, +8 authors R. Tielert
  • Engineering
  • ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference
  • 1989
A test device used for the development of a 16Mbit DRAM is described. It allows to compare different architectural options on one chip, such as different numbers of cells per bitline, or differentExpand
Bidirectional matched global bit line scheme for high density DRAMs
A new bit line organization, called Bidirectional Matched Global Bit Line (BMGB) scheme, is designed to overcome the difficulties in layout implementation and the high susceptibility to noise ofExpand
...
1
2
3
...

References

SHOWING 1-3 OF 3 REFERENCES
A 4-Mbit DRAM with trench-transistor cell
An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches.Expand
Circuit technologies for 16Mb DRAMs
  • T. Mano, T. Matsumura, +7 authors H. Namatsu
  • Computer Science
  • 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
  • 1987
THIS PAPER WILL DESCRIBE circuit technologies not only necessary for submicron ULSl memories, but also for customized ULSIs including RAM blocks. Key circnlts proposed here are an on-chip errorExpand
SCC (Surrounded Capacitor Cell) Structure for DRAM