A 16mb Dram with an Open Bit-Line Architecture

  title={A 16mb Dram with an Open Bit-Line Architecture},
  author={M. Inoue and H. Kotani and T. Yamada and H. Yamauchi and A. Fujiwara and J. Matsushima and H. Akamatsu and M. Fukumoto and M. Kubota and I. Nakao and N. Aoi and G. Fuse and S. Ogawa and S. Odanaka and A. Ueno and H. Yamamoto},
  journal={1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers},
  • M. Inoue, H. Kotani, +13 authors H. Yamamoto
  • Published 1988
  • Engineering, Computer Science
  • 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers
THIS PAPER WILL COVER A 16Mb DRAM with a 6511s RAS access time and 5.4mm x 17.38mm (93.85mm2) chip in a 300mil dual-in-line package. The chip was fabricated in 0 . 5 ~ N-well CMOS technology with double-poly, single-polycide and double-metal. To package a 16Mb DRAM in a 300mil DIP, the memory cell size has t o be less than 4pm2 maintaining a capacitance large enough for alpha-particle-induced soft error tolerance and the stable operation. Open bit-line architecture can provide a small geometry… Expand
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