A 16Kb electrically erasable nonvolatile memory
@article{Johnson1980A1E, title={A 16Kb electrically erasable nonvolatile memory}, author={W. Johnson and G. Perlegos and A. L. Renninger and Georg Kuhn and T. R. Ranganath}, journal={1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers}, year={1980}, volume={XXIII}, pages={152-153} }
A16K(2K×8) bit electrically-erasable nonvolatile memory (E2PROM) employing oxides less than 200 Å thick through which electrons tunnel toward or away from a floating polysilicon gate, will be covered.
49 Citations
Hot Carrier Design Considerations in MOS Nonvolatile Memories
- Engineering
- 1992
Floating-gate type nonvolatile semiconductor memories (NVSMs) were first introduced and applied by Kahng and Sze in 1967 [1]. The metal-nitride-oxide-silicon (MNOS) structure was first reported by…
A new architecture of NVRAM
- Computer Science1987 Symposium on VLSI Circuits
- 1987
High density EEPROMs beyond 04 K have already been introduced into the market. These EEPROMs' application, however, is limited because of lack of erase/write endurance and a long programming time.…
A high density floating-gate EEPROM cell
- Engineering1981 International Electron Devices Meeting
- 1981
An electrically erasable PROM cell is described which is implemented in a N-channel double polysilicon gate process. The cell is composed of a double poly floating-gate memory device and a select…
A 5V-only 16K EEPROM utilizing oxynitride dielectrics and EPROM redundancy
- Engineering1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
- 1982
This paper will describe an N-channel2K x 8 EEPROM where reading, writing and erasing operations are from a single 5V supply, achieved through a low-power cell design utilizing oxynitride tunnel dielectric and through internal charge pump circuitry for voltage multiplication.
Flash Memories: An Overview
- Computer Science
- 1999
Solid-state memory devices which retain information once the power supply is switched off are called “nonvolatile” memories, and the user can program the information by blowing fusible links or antifuses, thus changing permanently the cell content.
An 80 ns 32K EEPROM using the FETMOS cell
- EngineeringIEEE Journal of Solid-State Circuits
- 1982
A 32K bit EEPROM using the FETMOS (floating-gate electron tunneling MOS) cell has achieved a typical access time of 80 ns and a die size of 20.6 mm/SUP 2/ using approximately 3 /spl mu/m feature…
Program and erase of NAND memory arrays
- Computer Science
- 2010
The purpose of NAND Flash memories as a non-volatile memory is to store the user data for years without requiring a supply voltage. The state of the art memory cell for this purpose in NAND Flash is…
Basics of Nonvolatile Semiconductor Memory Devices
- Biology
- 1998
This chapter contains sections titled: Introduction Basic Principles and History of NVM Devices Basic Programming Mechanisms Basic NVSM Memory Products Basic NVSM Devices Presently in Use Basic NVSM…
Chapter 1 Basics of Nonvolatile Semiconductor Memory Devices
- Engineering
- 2005
Since the very first days of the mid-1960s, when the potential of metal-oxide semiconductor (MOS) technology to realize semiconductor memories with superior density and performance than would ever be…
A Novel CMOS Compatible Top-Floating-Gate Flash EEPROM Cell
- Engineering
- 2002
A novel nonvolatile memory (NVM) Top-floating-gate (TFG) flash device is demonstrated in a CMOS technology which can be implemented as a stand alone device, or with additional benefit as an embedded…
References
SHOWING 1-7 OF 7 REFERENCES
A 256-bit nonvolatile static RAM
- Physics1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
- 1978
A 32 × 8-bit nonvolatile RAM that can be operated as a normal static RAM at 5V will be covered. Nonvolatile Information storage is achieved by raising the power supply to 15V before turning off.
A 16Kb electrically erasable programmable ROM
- Engineering1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
- 1979
This paper will describe an I hK (2K x 8) EEPROM using N-channel Si-gate MNOS technology, which offers such advantages as on-board reprogrammability, no UV light and low package cost.
DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology
- EngineeringIEEE Transactions on Electron Devices
- 1977
Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional…
Electrically alterable hot-electron injection floating gate MOS memory cell with series enhancement
- Engineering1978 International Electron Devices Meeting
- 1978
An electrically alterable, floating gate, non-volatile memory transistor has been developed, having a cell area of under 500µ2, and using an advanced n-channel, polysilicon gate process. Cell…
Technology of a new n-channel one-transistor EAROM cell called SIMOS
- EngineeringIEEE Transactions on Electron Devices
- 1977
The structure and technology of a new nonvolatile charge-storage device are described. The stacked-gate injection MOS (SIMOS) device is an n-channel MOS transistor with a control gate stacked on the…
Fowler‐Nordheim Tunneling into Thermally Grown SiO2
- Physics
- 1969
Electronic conduction in thermally grown SiO2 has been shown to be limited by Fowler‐Nordheim emission, i.e., tunneling of electrons from the vicinity of the electrode Fermi level through the…
High performance, MOS EPROMs using a stacked-gate cell
- Engineering1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
- 1977