A 160 Mpixel/s IDCT processor for HDTV


28 fEEE Micro A fabricated, tested, fully functional40-MHz device perfonns the 8x8 inverse discrete cosine transform for digital HDlV decoders. It converts four I4-bit OCT coeffi cients into four ll-bit pixel values each cycle. Fixed-coefficient multiplier Walla ce trees (in which partial products are rounded before summation) help compute the inner products. The 3I,OOO-gate device was implemented in a 10.5-mm die using a I-micron CMOS array-based process.

DOI: 10.1109/40.166710

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@article{Ruetz1992A1M, title={A 160 Mpixel/s IDCT processor for HDTV}, author={Peter A. Ruetz and Po Tong}, journal={IEEE Micro}, year={1992}, volume={12}, pages={28-32} }