A 16 384-bit dynamic RAM

@article{Ahlquist1976A13,
  title={A 16 384-bit dynamic RAM},
  author={C. Ahlquist and J. Breivogel and J. T. Koo and J. L. McCollum and W. G. Oldham and A. Renninger},
  journal={IEEE Journal of Solid-State Circuits},
  year={1976},
  volume={11},
  pages={570-574}
}
  • C. Ahlquist, J. Breivogel, +3 authors A. Renninger
  • Published 1976
  • Computer Science
  • IEEE Journal of Solid-State Circuits
  • A 16-kbit dynamic RAM is described which is TTL compatible on all pins, and fits a standard 16-pin package. A single-transistor storage cell is used which occupies 455 /spl mu/m/SUP 2/. The device is fabricated in n-channel two-layer polysilicon gate technology using conventional design rules. The chip size is 145 by 234 mils. A low-power sense amplifier is used for each 64 memory cells. A special refresh mode is possible in which all 256 sense amplifiers are active, and the entire memory can… CONTINUE READING
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    References

    SHOWING 1-10 OF 10 REFERENCES
    8192-bit block addressable CCD memory
    • 5
    Design of a 16384-bit serial charge-coupled memory device
    • 11
    A TTL compatible 4096-bit N-channel RAM
    • 10
    Design of 16384 bit serial charged coupled memory Ievicej
    • IEEE J. Solid-State Circuits, vol
    • 1976
    Storage array and seine/ efresh circuits for single transistor cells,
    • IEEE J. Solid-State
    • 1973
    S’62-M’72) was born in Shanghai
    • China- on February
    • 1941