A 15MIPS 32b microprocessor

  title={A 15MIPS 32b microprocessor},
  author={Jeff Yetter and Mark E. Forsyth and William S. Jaffe and Darius Tanksalvala and J. K. Wheeler},
  journal={1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  • J. Yetter, M. Forsyth, J. Wheeler
  • Published 1987
  • Computer Science
  • 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
A Reduced Instruction Set Computer using direct hardware instruction decode and 3-stage pipelined execution will be described. At an operating frequency of 30MHz, a 120Mbytes/s transfer rate on an external cache/coprocessor interface is achieved. NMOS technology is used to implement 115K transistors on an 8.4mm square chip. 

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