A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications

@article{Palmer2007A16,
  title={A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications},
  author={Robert Palmer and John Poulton and William J. Dally and John G. Eyles and Andrew M. Fuller and Trey Greer and Mark Horowitz and M. Kellam and F. Quan and F. Zarkeshvari},
  journal={2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  year={2007},
  pages={440-614}
}
A power-efficient 6.25Gb/s transceiver in 90nm CMOS for chip-to-chip communication is presented, it dissipates 2.2mW/Gb/s operating at a BER of <10-15 over a channel with -15dB attenuation at 3.125GHz. A shared LC-PLL, resonant clock distribution, a low-swing voltage-mode transmitter, a low-power phase rotator, and a software-based CDR and an adaptive equalizer are used to reduce power 

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