A 14 nm FinFET 128 Mb SRAM With V $_{\rm MIN}$ Enhancement Techniques for Low-Power Applications

  title={A 14 nm FinFET 128 Mb SRAM With V \$_\{\rm MIN\}\$ Enhancement Techniques for Low-Power Applications},
  author={Taejoong Song and Woojin Rim and Jonghoon Jung and Giyong Yang and Jaeho Park and Sunghyun Park and Yongho Kim and Kang-Hyun Baek and Sanghoon Baek and Sang-Kyu Oh and Jinsuk Jung and Sungbong Kim and Gyu-Hong Kim and Jintae Kim and Young-Keun Lee and Sang-Pil Sim and Jong Shik Yoon and Kyu-Myung Choi and Hyo-Sig Won and Jaehong Park},
  journal={IEEE Journal of Solid-State Circuits},
Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 μm2 and a 0.080 μm2 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve VMIN of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the VMIN of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully… CONTINUE READING
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