A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter

@article{Singer1996A11,
  title={A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter},
  author={L. Singer and T. Brooks},
  journal={1996 Symposium on VLSI Circuits. Digest of Technical Papers},
  year={1996},
  pages={94-95}
}
A 14-bit 10-MHz sampling analog-to-digital converter has been realized without calibration in a double-poly 0.8 /spl mu/m CMOS process. The ADC utilizes a 4-stage pipelined architecture with a wide-band sample-and-hold amplifier and achieves the highest resolution reported to date at 10 MHz. The chip occupies a die area of 19 mm/sup 2/, uses a single 5 V supply voltage, and dissipates only 210 mW. Measured DNL and INL are /spl plusmn/0.7 LSB and /spl plusmn/2.5 LSB, respectively. The SNR and… CONTINUE READING
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References

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A Power Optimized 13-Bit SMsamples/s Pipelined Analog to Digital Converter in 1.2 pm CMOS,

I D.W. Cline, P. R. Gray
Proc. IEEE CICC, • 1995

Digital - Domain Calibration of Multistep Analog - to - Digital Converters

P. R. Gray, B.-S. Song
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