A 14 b 40 MSample/s pipelined ADC with DFCA

@article{Yu2001A1B,
  title={A 14 b 40 MSample/s pipelined ADC with DFCA},
  author={P. C. Yu and Samuel Shehata and Amit A Joharapurkar and Pranshu Chugh and A. Bugeja and Xiaohong Du and Sung-Ung Kwak and Y. Papantonopoulous and Turker Kuyel},
  journal={2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)},
  year={2001},
  pages={136-137}
}
A DAC and feedback capacitor averaging (DFCA) technique used in a pipelined ADC achieves 84 dB SFDR and 74 dB SNR. Also external mismatch noise cancellation digitally improves the SNR. Excluding output drivers, the 0.6 μm double-poly BiCMOS ADC dissipates 860 mW from 3.3 V supply. 
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References

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A High SFDK Pipelind ADC Architecture with Improved SNR Using a Digital Mismatch Noise Canrellatian ‘lkhnique”

P. C. Yu
US Patent Pendinc (filed Doc • 1999

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