A 14 b 40 MSample/s pipelined ADC with DFCA

  title={A 14 b 40 MSample/s pipelined ADC with DFCA},
  author={P. C. Yu and Samuel Shehata and Amit A Joharapurkar and Pranshu Chugh and A. Bugeja and Xiaohong Du and Sung-Ung Kwak and Y. Papantonopoulous and Turker Kuyel},
  journal={2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)},
A DAC and feedback capacitor averaging (DFCA) technique used in a pipelined ADC achieves 84 dB SFDR and 74 dB SNR. Also external mismatch noise cancellation digitally improves the SNR. Excluding output drivers, the 0.6 μm double-poly BiCMOS ADC dissipates 860 mW from 3.3 V supply. 
Highly Cited
This paper has 23 citations. REVIEW CITATIONS


Publications citing this paper.
Showing 1-10 of 19 extracted citations

Capacitor-Swapping Cyclic A/D Conversion Techniques With Reduced Mismatch Sensitivity

IEEE Transactions on Circuits and Systems II: Express Briefs • 2008
View 3 Excerpts
Highly Influenced

A background calibration technology for capacitance mismatch in pipelined ADCs with 2.5-bit/stage MDAC

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) • 2016
View 1 Excerpt

Histogram Based Deterministic Digital Background Calibration for Pipelined ADCs

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems • 2014

A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1

IEEE Transactions on Circuits and Systems I: Regular Papers • 2013
View 1 Excerpt

Design and Implementation of 7-bit Pipeline Analog to Digital Converter

2012 Fourth International Conference on Computational Intelligence and Communication Networks • 2012
View 1 Excerpt

A 12-Bit 200-MHz CMOS ADC

IEEE Journal of Solid-State Circuits • 2009

A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse

IEEE Journal of Solid-State Circuits • 2007
View 1 Excerpt


Publications referenced by this paper.

A High SFDK Pipelind ADC Architecture with Improved SNR Using a Digital Mismatch Noise Canrellatian ‘lkhnique”

P. C. Yu
US Patent Pendinc (filed Doc • 1999

Similar Papers

Loading similar papers…