A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration


We discuss a 14 bit 1 GS/s RF sampling pipelined ADC that utilizes correlation-based background calibration to correct the inter-stage gain, settling and memory errors. To improve the sampling linearity and RF sampling performance, the ADC employs input distortion cancellation and a digital background calibration technique to compensate for the non-linear… (More)
DOI: 10.1109/JSSC.2014.2361339


13 Figures and Tables


Citations per Year

Citation Velocity: 19

Averaging 19 citations per year over the last 3 years.

Learn more about how we calculate this metric in our FAQ.