A 12b 50MS/s 3.5mW SAR assisted 2-stage pipeline ADC

@article{Lee2010A15,
  title={A 12b 50MS/s 3.5mW SAR assisted 2-stage pipeline ADC},
  author={Chun Chen Lee and Michael P. Flynn},
  journal={2010 Symposium on VLSI Circuits},
  year={2010},
  pages={239-240}
}
A 12b 50MS/s ADC is presented that pipelines a first stage 6b MDAC with a second stage 7b SAR ADC. The first stage uses a low-power SAR architecture for the sub-ADC, to achieve the large 6b stage resolution. A “half-gain” MDAC reduces the output swing and increases the closed-loop bandwidth of the op-amp in the first stage. This ADC consumes 3.5mW from a 1.3V supply, achieves an ENOB of 10.4b at Nyquist, and an FOM of 52fJ/conversion-step. 
Highly Cited
This paper has 44 citations. REVIEW CITATIONS
32 Citations
5 References
Similar Papers

Citations

Publications citing this paper.
Showing 1-10 of 32 extracted citations

References

Publications referenced by this paper.
Showing 1-5 of 5 references

Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications

  • S. H. Lewis
  • IEEE Trans. Circuits Syst. II, vol. 39, pp. 516…
  • 1992
1 Excerpt

Similar Papers

Loading similar papers…