A 12b 180MS/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC

@article{Zhong2017A11,
  title={A 12b 180MS/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC},
  author={Jianyu Zhong and Yan Zhu and Chi-Hang Chan and Sai-Weng Sin and U Seng-PanBen and Rui Paulo Martins},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  year={2017},
  volume={64},
  pages={1684-1695}
}
This paper presents a 12b 180 MS/s 0.068 mm2 $2\times$ time-interleaved pipelined-SAR analog-to-digital conver-ter (ADC) with gain and offset calibrations fully embedded on-chip. The proposed binary-search gain calibration (BSGC) technique corrects the inter-stage gain error caused by the open-loop residue amplifier. The BSGC, fully integrated into the second-stage SAR ADC, contributes to a compact area. We improve the noise performance by implementing a merged-residue-DAC operation in the… CONTINUE READING