A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO

@article{Ru2013A12,
  title={A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO},
  author={Zhiyu Ru and Paul F. J. Geraedts and E. A. M. Klumperink and Xin He and Bram Nauta},
  journal={2013 Symposium on VLSI Circuits},
  year={2013},
  pages={C194-C195}
}
An integer-N digital PLL architecture is presented that simplifies the critical phase path using a sub-sampling binary (bang-bang) phase detector. Two power-efficient techniques are presented that can reduce DCO frequency tuning step by voltage-domain and time-domain (pulse-width) modulating the DCO LSB varactors. Measurement shows 210fs RMS jitter at 11.8GHz DCO frequency and 6mW power. 
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