A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique

@article{Lin2014A12,
  title={A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique},
  author={Chin-Yu Lin and Tai-Cheng Lee},
  journal={2014 Symposium on VLSI Circuits Digest of Technical Papers},
  year={2014},
  pages={1-2}
}
A 210 MS/s dual-channel 12-bit analog-to-digital converter (ADC) employing a pipelined successive approximation (SAR) architecture is presented. The ADC is partitioned into 3 stages with passive residue transferring between the 1st and the 2nd stages and active residue amplification between the 2nd and the 3rd stages. The ADC consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.48 dB at a 5-MHz input and 60.1 dB near Nyquist-rate. 
Highly Cited
This paper has 21 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 14 extracted citations

A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer

2015 IEEE Asian Solid-State Circuits Conference (A-SSCC) • 2015
View 3 Excerpts
Highly Influenced

A 12b 180MS/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC

IEEE Transactions on Circuits and Systems I: Regular Papers • 2017
View 2 Excerpts

Two-Step Residue Transfer Technique for High-Speed Pipeline A/Ds

2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) • 2017
View 2 Excerpts

A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC) • 2016
View 1 Excerpt

References

Publications referenced by this paper.
Showing 1-6 of 6 references

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

2010 IEEE International Solid-State Circuits Conference - (ISSCC) • 2010
View 2 Excerpts

A 12b 50MS/s 3.5mW SAR assisted 2-stage pipeline ADC

2010 Symposium on VLSI Circuits • 2010
View 1 Excerpt

A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS

IEEE Custom Integrated Circuits Conference 2010 • 2010
View 1 Excerpt

Murmann “ A 12 - bit , 200 - MS / s , 11 . 5 - mW Pipeline ADC using Pulsed Bucket Brigade Front - End , ” in

M. Kramer Dolev, B.
Proc . VLSI Circuits Symp .

Similar Papers

Loading similar papers…