A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique

  title={A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique},
  author={Chin-Yu Lin and Tai-Cheng Lee},
  journal={2014 Symposium on VLSI Circuits Digest of Technical Papers},
A 210 MS/s dual-channel 12-bit analog-to-digital converter (ADC) employing a pipelined successive approximation (SAR) architecture is presented. The ADC is partitioned into 3 stages with passive residue transferring between the 1st and the 2nd stages and active residue amplification between the 2nd and the 3rd stages. The ADC consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.48 dB at a 5-MHz input and 60.1 dB near Nyquist-rate. 
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