A 10b 250MS/s binary-weighted current-steering DAC

@article{Deveugele2004A12,
  title={A 10b 250MS/s binary-weighted current-steering DAC},
  author={Jurgen Deveugele and Michiel S. J. Steyaert},
  journal={2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)},
  year={2004},
  pages={362-532 Vol.1}
}
A 10b binary-weighted current-steering DAC has over 60dB SFDR at 250 MS/s for signals from DC to Nyquist. The chip draws 4mW from a dual 1.5/1.8V supply (plus load currents). Active area is less than 0.35 mm/sup 2/ in a standard 0.18/spl mu/m 1P5M 1.8V CMOS process, and both INL and DNL are below 0.1LSB. 
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