A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference

@article{Liu2017A12,
  title={A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference},
  author={Maoqiang Liu and Arthur H. M. van Roermund and Pieter Harpe},
  journal={ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference},
  year={2017},
  pages={231-234}
}
Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops during the conversion due to passive charge sharing, causing non-binary DAC switching steps… CONTINUE READING

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