A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

@article{Liu2010A11,
  title={A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation},
  author={Chun-Cheng Liu and S. Chang and Guan-Ying Huang and Ying-Zu Lin and Chung-Ming Huang and Chih-Hao Huang and Linkai Bu and C. Tsai},
  journal={2010 IEEE International Solid-State Circuits Conference - (ISSCC)},
  year={2010},
  pages={386-387}
}
  • Chun-Cheng Liu, S. Chang, +5 authors C. Tsai
  • Published 2010
  • Engineering, Computer Science
  • 2010 IEEE International Solid-State Circuits Conference - (ISSCC)
In recent years, due to the improvements in CMOS technologies, medium resolution (8 to 10b) SAR ADCs have been able to achieve sampling rates of several tens of MS/s with excellent power efficiency and small area [1]–[4. [...] Key Result The ADC achieves 100MS/s while consuming only 1.13mW.Expand
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