A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing

@article{Noguchi2007A1N,
  title={A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing},
  author={Hiroki Noguchi and Yusuke Iguchi and Hidehiro Fujiwara and Yasuhiro Morita and Koji Nii and Hiroshi Kawaguchi and Masahiko Yoshimoto},
  journal={IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)},
  year={2007},
  pages={107-112}
}
We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is consumed only when a readout datum is changed. This feature is suitable to video processing since… CONTINUE READING
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