A 10MHz to 600MHz low jitter CMOS PLL for clock multiplication

@article{Fan2008A1T,
  title={A 10MHz to 600MHz low jitter CMOS PLL for clock multiplication},
  author={Bing Fan and Luo-sheng Li and Zi-qiao Chu and Dong-hui Wang and Chao-Huan Hou},
  journal={2008 9th International Conference on Solid-State and Integrated-Circuit Technology},
  year={2008},
  pages={1929-1932}
}
This paper describes a phase-locked loop (PLL) designed for clock multiplication. The PLL has a locking range from 10 MHz to 600 MHz at 1.8 V power supply. It has a very low peak-to-peak jitter which less than 50 ps at 150 MHz output frequency. It has been fabricated in a 0.18 ¿m CMOS process. The area of the active layout of the PLL is 560 ¿m * 400 ¿m, and… CONTINUE READING