A 10Gb/s/ch 50mW 120/spl times/130/spl mu/m/sup 2/ clock and data recovery circuit

@article{Kaeriyama2003A15,
  title={A 10Gb/s/ch 50mW 120/spl times/130/spl mu/m/sup 2/ clock and data recovery circuit},
  author={Shunichi Kaeriyama and Masayuki Mizuno},
  journal={2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.},
  year={2003},
  pages={70-478 vol.1}
}
A 10Gb/s clock and data recovery circuit for SerDes macro uses half the power and a quarter the die size of prior art. In 0.15/spl mu/m CMOS the CDR dissipates 50mW in an area of 120/spl times/130/spl mu/m/sup 2/ while maintaining a 10Gb/s bandwidth per channel. Jitter tolerance is also improved and the influence of PVT variations is reduced. 
Highly Cited
This paper has 20 citations. REVIEW CITATIONS

From This Paper

Topics from this paper.

Citations

Publications citing this paper.
Showing 1-10 of 16 extracted citations

References

Publications referenced by this paper.
Showing 1-2 of 2 references

A 100Gb/s Tranceiver with GND-VDD Common- Mode Receiver and Flexible Multi-Channel Aligner

  • K. Tanaka
  • ISSCC Dig. of Tech. Papers, pp.264-265, 2002.
  • 2002
Highly Influential
13 Excerpts

Similar Papers

Loading similar papers…