A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control

@article{Choi2008A1S,
  title={A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control},
  author={M. Choi and Sung-No Lee and Seung-Bin You and Wang-Seup Yeum and Ho-Jin Park and Jae-Whui Kim and H. Lee},
  journal={2008 IEEE Custom Integrated Circuits Conference},
  year={2008},
  pages={89-92}
}
  • M. Choi, Sung-No Lee, +4 authors H. Lee
  • Published 2008
  • Physics, Computer Science
  • 2008 IEEE Custom Integrated Circuits Conference
  • A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65 nm CMOS process, dissipates 15 mW and occupies an active die area of 0.28 mm2. A post integration time control (PITC) technique is proposed for calibration of the RC time constant variation of the continuous-time integrator. In addition, a jitter insensitive pulse generator (JIPG) circuit overcomes the degradation of SNR due to the feedback DAC clock jitter. The measured SNR and DR are 101 dB and THD… CONTINUE READING
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