A 100 nm node CMOS technology for practical SOC application requirement

@article{Ono2001A1N,
  title={A 100 nm node CMOS technology for practical SOC application requirement},
  author={Akito Ono and Katsuhiko Fukasaku and Takayuki Hirai and Satoru Koyama and Mariko Makabe and Takeshi Matsuda and Masafumi Takimoto and Y. Kunimune and Nobuyuki Ikezawa and Yoshiteru Yamada and F. Koba and Kiyotaka Imai and Nozomi Nakamura},
  journal={International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)},
  year={2001},
  pages={22.5.1-22.5.4}
}
Reports a 1.0 V operation 100 nm technology node CMOS technology for generic SOC application. We have estimated that for practical SOC chip/package design, target spec of both I/sub OFF/ and I/sub G/ must be below 5 nA//spl mu/m in view of heat generation issue. The key point is how to obtain higher drive current under this I/sub OFF//I/sub G/ restriction. Taking this criteria into account, we optimized 1) the gate dielectric formation sequence consisting of RTH treatment and radical… CONTINUE READING

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