A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications

@article{Toyoda2007A1A,
  title={A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications},
  author={Hidehiro Toyoda and Shinji Nishimura and Michitaka Okuno and Matsuaki Terada},
  journal={IEICE Trans. Electron.},
  year={2007},
  volume={90-C},
  pages={1957-1963}
}
A high-speed physical-layer architecture for next-generation higher-speed Ethernet for VSR and backplane applications was developed. VSR and backplane networks provide 100-Gb/s data transmission in "mega data centers" and blade servers, which have new and broad potential markets of LAN technologies. It supports 100-Gb/s-throughput, high-reliability, and low-latency data transmission, making it well suited to VSR and backplane applications for intra-building and intra-cabinet networks. Its links… 

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References

SHOWING 1-10 OF 11 REFERENCES
100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet
TLDR
Testing of this physical-layer architecture for Ethernet in a field programmable gate array circuit demonstrated that it can provide 100-Gb/s data communication with a 590k gate circuit, which is small enough for implementation in a single LSI circuit.
A 100-Gb-Ethernet subsystem for next-generation metro-area network
TLDR
An ultra high-speed Ethernet subsystem, which realizes 100-Gb/s throughput and transmission up to 40 km, is examined for next-generation metro-area networks, and a 64B/66B code-sequence-based de-skewing mechanism is proposed, and its effectiveness to realize low-latency compensation of the inter-lane skew is shown.
100-Gb/s DQPSK Transmission Experiment Without OTDM for 100G Ethernet Transport
In order to realize a future 100-Gb Ethernet (100 GbE) transport, 100-Gb/s transmission without 100-GHz-class electronics and optical time-division-multiplexing technique was demonstrated. By using a
107-Gb/s optical ETDM transmitter for 100G Ethernet transport
Using optical duobinary modulation, we demonstrate the first electrical time-division multiplexed (ETDM) optical transmitter at 107 Gb/s, suitable for serial transport of 100G Ethernet. (2 pages)
10 × 107 Gb/s electronically multiplexed NRZ transmission at 0.7 bits/s/Hz over 1000 km non-zero dispersion fiber
We demonstrate wavelength-division multiplexed transmission of 10 electronically multiplexed 107-Gb/s non return-to-zero (NRZ) channels (1 Tb/s at a spectral efficiency of 0.7 bits/s/Hz) over 1000 km
PMD architecture with skew compensation mechanism for parallel link IEEE 802.3 Higher Speed Study Group
  • PMD architecture with skew compensation mechanism for parallel link IEEE 802.3 Higher Speed Study Group
  • 2006
Forward error correction for 10 GBASE-KR
  • Forward error correction for 10 GBASE-KR
IEEE Std
  • IEEE Std
  • 2005
PMD architecture with skew compensation mechanism for parallel link
  • IEEE 802.3 Higher Speed Study Group, http://www.ieee802.org/3/hssg/public/ nov06/nishimura 01 1106.pdf, Nov. 2006.
  • 2006
...
...