A 10-pJ/instruction, 4-MIPS micropower DSP for sensor applications

@article{Ickes2008A14,
  title={A 10-pJ/instruction, 4-MIPS micropower DSP for sensor applications},
  author={Nathan Ickes and D. Finchelstein and A. P. Chandrakasan},
  journal={2008 IEEE Asian Solid-State Circuits Conference},
  year={2008},
  pages={289-292}
}
We describe a micropower DSP intended for medium bandwidth microsensor applications (such as acoustic sensing and tracking) which achieves 4 MIPS performance at 40 muW (10 pJ per instruction). Architectural optimizations for energy efficiency include a custom CPU instruction set, miniature instruction cache, hardware accelerator cores for FIR filter and FFT operations, and extensive power gating of both logic and memory. 
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