A 10-bit Current-steering DAC in 0 . 35-μ m CMOS Process

@inproceedings{Cui2009A1C,
  title={A 10-bit Current-steering DAC in 0 . 35-μ m CMOS Process},
  author={Zhi-Yuan Cui and H Piao and Nam-Soo Kim},
  year={2009}
}
A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-μm CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs… CONTINUE READING

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