A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

@article{Liu2010A15,
  title={A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure},
  author={Chun-Cheng Liu and Soon-Jyh Chang and Guan-Ying Huang and Ying-Zu Lin},
  journal={IEEE Journal of Solid-State Circuits},
  year={2010},
  volume={45},
  pages={731-740}
}
This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the… 
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922 Citations

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  • Engineering, Business
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This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that is combined with a parasitic-compensated split-capacitor DAC that also has an improved capacitor matching.
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