A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

@article{Liu2010A15,
  title={A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure},
  author={Chun-Cheng Liu and Soon-Jyh Chang and Guan-Ying Huang and Ying-Zu Lin},
  journal={IEEE Journal of Solid-State Circuits},
  year={2010},
  volume={45},
  pages={731-740}
}
This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the… 
10-bit 30-MS/s SAR ADC Using a Switchback Switching Method
TLDR
The proposed switchback switching method does not consume any power at the first digital-to-analog converter switching, which can reduce the power consumption and design effort of the reference buffer.
A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 μm CMOS
This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18 μm 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a
A 10-bit 10-MS/s 0.18-㎛ CMOS Asynchronous SAR ADC with split-capacitor based differential DAC
TLDR
This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital- to-analog converter (DAC) and the time-domain comparator with an offset calibration technique is used to achieve a high resolution.
A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 μm CMOS*
This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18 μm 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a
A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme
TLDR
This paper presents a 10-bits successive approximation register analog-to-digital converter (SAR ADC) for low-power applications that achieved a reduction in the number of the capacitors and the controlled switches compared with those required in the conventional SAR ADC design.
A 10-bit 100-MS/s power-efficient asynchronous SAR ADC
This paper presents a power-efficient 100-MS/s, 10-bit asynchronous successive approximation register (SAR) ADC. It includes an on-chip reference buffer and the total power dissipation is 6.8 mW. To
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications
TLDR
An energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications is presented and a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window.
A low-power 10-bit 50-MS/s SAR ADC using a parasitic-compensated split-capacitor DAC
  • Wei Guo, S. Mirabbasi
  • Engineering, Business
    2012 IEEE International Symposium on Circuits and Systems
  • 2012
TLDR
This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that is combined with a parasitic-compensated split-capacitor DAC that also has an improved capacitor matching.
A 9-Bit 70-MS/s Two-Stage SAR ADC With Passive Residue Transfer
TLDR
A two-stage successive approximation register analog-to-digital converter (ADC) is reported, and it is shown this technique reduces the transfer and the fine stage switching energy by 75%.
...
...

References

SHOWING 1-10 OF 25 REFERENCES
A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS
TLDR
An asynchronous analog-to-digital converter (ADC) based on successive approximation is used to provide a high-speed (600-MS/s) and medium-resolution (6-bit) conversion which allows its use in RF subsampling applications.
500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC
A 500-MS/s 5-bit ADC for UWB applications has been fabricated in a 65-nm CMOS technology using no analog-specific processing options. The time-interleaved successive approximation register (SAR)
A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process
TLDR
A 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method that reduces the average switching energy by about 81% and achieves an SNDR of 52.78dB.
A 8-bit 500-KS/s low power SAR ADC for bio-medical applications
This paper presents a successive approximation register analog-to-digital converter (SAR ADC) design for bio-medical applications. An energy-saving switching sequence technique is proposed to achieve
A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization
  • Wenbo Liu, Yuchun Chang, Y. Chiu
  • Computer Science
    2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers
  • 2009
TLDR
This work showcases a digital background-equalization technique to treat the path-mismatch problem as well as individual ADC nonlinearities in time-interleaved SAR ADC arrays.
A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS
TLDR
An asynchronous analog-to-digital converter based on successive approximation is used to provide a high-speed (600-MS/s) and medium-resolution (6-bit) conversion which allows its use in RF subsampling applications.
An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit
TLDR
This paper describes an 8-bit pipelined analog-to-digital converter (ADC) using a mixed-mode sample-and-hold (S/H) circuit at the front-end that achieves 54-dB spurious free dynamic range and 45-dB signal- to-noise and distortion ratio.
1-V 9-bit pipelined switched-opamp ADC
TLDR
A 9-bit 1.0-V pipelined analog-to-digital converter has been designed using the switched-opamp technique, and three low-voltage circuit blocks are developed, including an improved common-mode feedback circuit for a switched opamp, and a fully differential comparator.
A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS
A time-interleaved ADC is presented with 16 channels, each consisting of a track-and-hold (T&H) and two successive approximation (SA) ADCs in a pipeline configuration to combine a high sample rate
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS
...
...