A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS

@article{Liu2015A1B,
  title={A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS},
  author={Chun-Cheng Liu and Che-Hsun Kuo and Ying-Zu Lin},
  journal={IEEE Journal of Solid-State Circuits},
  year={2015},
  volume={50},
  pages={2645-2654}
}
This paper presents a low-cost successive approximation register (SAR) analog-to-digital converter (ADC) for IEEE 802.11 ac applications. In this paper, a binary-scaled recombination capacitor weighting method is disclosed. The digital sub-blocks in this ADC are composed of standard library logic cells. The prototype is fabricated in a 1P8M 20 nm CMOS technology. At 0.9 V supply and 160 MS/s, the ADC consumes 0.68 mW. It achieves an SNDR of 57.7 dB and 57.13 dB at low and Nyquist input… CONTINUE READING

Citations

Publications citing this paper.
SHOWING 1-5 OF 5 CITATIONS

A high speed pipeline ADC with 78-dB SFDR in 0.18 um BiCMOS

  • 2016 International Symposium on Integrated Circuits (ISIC)
  • 2016
VIEW 4 EXCERPTS
CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

A 10-Bit 5 MS/s VCO-SAR ADC in 0.18- $\mu$ m CMOS

  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • 2019
VIEW 1 EXCERPT
CITES BACKGROUND

A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks

  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • 2018
VIEW 1 EXCERPT
CITES METHODS

Redundant SAR ADCs with Split-capacitor DAC

  • 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
  • 2018
VIEW 2 EXCERPTS
CITES METHODS

References

Publications referenced by this paper.
SHOWING 1-10 OF 22 REFERENCES

A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS

  • 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
  • 2007
VIEW 9 EXCERPTS
HIGHLY INFLUENTIAL

A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS

  • 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)
  • 2014
VIEW 1 EXCERPT

A 90 GS/s 8 b 667 mW 64 interleaved SAR ADC n 32 nm digital SOI

L. Kull, T. Toifl, +7 authors Y. Leblebici
  • IEEE ISSCC Dig. Tech. Papers, 2014, pp. 378–379.
  • 2014
VIEW 1 EXCERPT

An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS

  • 2014 Symposium on VLSI Circuits Digest of Technical Papers
  • 2014

A 10 b 200 MS/s 0.82 mW SAR ADC in 40 nm

G. Y. Huang, S. J. Chang, Y. Z. Lin, C. C. Liu, C. P. Huang
  • Proc. IEEE A-SSCC, 2013, pp. 289–292.
  • 2013

Similar Papers

Loading similar papers…