A 10-bit 10Ms/s pipeline cyclic ADC based on β-expansion


This paper presents a 10-bit, 10Ms/s pipeline cyclic analog-to-digital converter (ADC) in 90nm CMOS technology. The proposed ADC is designed and fabricated in 3-stage pipeline structure, and each pipeline stage is a non-binary cyclic ADC based on β-expansion. The output bit-number of stages is selected as 4-4-8 bits according to the considerations of chip area, conversion speed and total power consumption. We also optimized the capacitor value and amplifier parameter of the MDAC at each stage to satisfy the required performance of ADC. The radix value of non-binary output code can be estimated with our proposed algorithm, and the 16-bit output non-binary-codes are converted to 10-bit binary-codes by off-chip processing. The redundancy of non-binary ADC tolerates the non-linearity errors of conversion so that required accuracy of analog components is dramatically relaxed. The prototype ADC achieves a measured SNDR of 61.07dB at 10Ms/s even with an amplifier with poor DC gain as low as 45dB. The measured DNL is +0.32/-0.61LSB and INL is +0.79/-0.67LSB at 311.3kHz input. The total power consumption of ADC is 4.7mW at 1.2V supply and it occupies an active area of 0.068mm2.

DOI: 10.1109/ISPACS.2015.7432783

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@article{Mishima2015A11, title={A 10-bit 10Ms/s pipeline cyclic ADC based on β-expansion}, author={Yuta Mishima and Toshiki Yamada and Asato Uchiyama and Tatsuji Matsuura and Hao San and Masao Hotta}, journal={2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)}, year={2015}, pages={294-298} }