A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

  title={A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS},
  author={Yan Zhu and C. Chan and U. Chio and S. Sin and U. Seng-Pan and R. Martins and F. Maloberti},
  journal={IEEE Journal of Solid-State Circuits},
  • Yan Zhu, C. Chan, +4 authors F. Maloberti
  • Published 2010
  • Physics, Computer Science
  • IEEE Journal of Solid-State Circuits
  • A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. [...] Key Method Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.Expand Abstract
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