A 10-bit, 1.8-GS/s Time-Interleaved Pipeline ADC

@article{Hakkarainen2007A11,
  title={A 10-bit, 1.8-GS/s Time-Interleaved Pipeline ADC},
  author={V{\"a}in{\"o} Hakkarainen and Arto Rantala and Mikko Aho and Jaana Riikonen and David Gomes-Martin and Markku {\AA}berg and Kari Halonen},
  journal={2007 14th IEEE International Conference on Electronics, Circuits and Systems},
  year={2007},
  pages={673-676}
}
In this paper, a 10-bit, 1.8-GS/s time-interleaved analog-to-digital converter (ADC) is presented. The ADC employs 24 parallel 10-bit pipeline ADCs to reach the conversion rate of 1.8 GS/s. Sampling clocks are generated by a delay-locked loop (DLL), which includes a calibration of timing skew. Offset and gain error are calibrated in order to overcome the effects of device mismatch within a channel ADC. The ADC, implemented with a 0.35-mum BiCMOS, achieves an effective number of bits (ENOB) of 7… CONTINUE READING

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