A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture

@article{Morioka2004A1F,
  title={A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture},
  author={Sumio Morioka and Akashi Satoh},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2004},
  volume={12},
  pages={686-691}
}
In this brief, we present a high-speed AES IP-core, which runs at 880 MHz on a 0.13-/spl mu/m CMOS standard cell library, and which achieves over 10-Gbps throughput in all encryption modes, including cipher block chaining (CBC) mode. Although the CBC mode is the most widely used and important, achieving such high throughput was difficult because pipelining and/or loop unrolling techniques cannot be applied. To reduce the propagation delays of the S-Box, the slowest function block, we developed… CONTINUE READING

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