A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

@article{Tomita2005A1R,
  title={A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS},
  author={Yukata Tomita and Masaya Kibune and Jun Ogawa and W. W. Walker and Hirotaka Tamura and Tomoko Kuroda},
  journal={IEEE Journal of Solid-State Circuits},
  year={2005},
  volume={40},
  pages={986-993}
}
A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched… CONTINUE READING
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